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# Positron's $5 Billion Bet Against HBM
- URL: https://www.edgewisely.com/positron-ai-875-million-series-c-lpddr5x-inference/
- Published: 2026-09-11T05:10:43.000Z
- Updated: 2026-09-11T05:19:16.000Z
- Description: How an $875 million round on commodity LPDDR5X memory challenges the HBM bottleneck that gates every AI accelerator shipping today.
- Author: John Karpentar
- Tags: Chips, Startups

**A chip startup just raised $875 million on the argument that the industry is rationing the wrong resource.**

The constraint on AI inference in 2026 is not floating-point math. It is memory — how much of it sits next to the compute, how fast it can be read, and how much of the world's supply of high-bandwidth memory you can actually buy. Nearly every accelerator on the market answers that with HBM stacked through advanced packaging, which means nearly every accelerator on the market queues behind the same two bottlenecks.

On September 10, Reno-based Positron AI [announced an $875 million Series C at a $5 billion post-money valuation](https://www.prnewswire.com/news-releases/positron-ai-raises-875-million-at-a-5-billion-valuation-to-bring-its-next-generation-inference-silicon-to-market-302874601.html?ref=edgewisely.com) to build inference silicon that skips HBM entirely. Its next-generation chips use LPDDR5X — the commodity memory in laptops and phones — and a great deal of it.

The bet is not that Positron can beat Nvidia at peak throughput. It is that for the specific job of serving very large models with very long context, buying enormous quantities of cheap memory beats rationing small quantities of expensive memory.

## The round, and what it buys

The financing came in two tranches. A $375 million Series C at a $3.5 billion pre-money valuation was co-led by NEA, Atreides Management, Valor Equity Partners, Andra Capital and Dylan Patel's SemiAnalysis Capital. A Series C-1 of up to $500 million was led by NEA and Jim Clark, the Silicon Graphics founder and Netscape co-founder. Qatar Investment Authority, DFJ Growth, Cisco Investments, Hudson River Trading and Naver Ventures also participated. Forest Baskett of NEA, Gavin Baker of Atreides, Thomas Jermoluk and Patel take board seats.

The capital is allocated against three concrete milestones — more specificity than most rounds of this size disclose, as [Converge Digest noted in its breakdown](https://convergedigest.com/positron-ai-raises-875m-asimov-inference-silicon/?ref=edgewisely.com). First, tape out **Asimov**, the next-generation silicon, on TSMC's N3P process at the end of 2026, with production in the second half of 2027\. Second, stand up a 2 MW-plus engineering data center and emulation platform. Third, ramp **Titan**, the system built from Asimov — including LPDDR5X supply commitments, which is the whole thesis expressed as a purchase order.

Asimov pairs Positron's compute architecture with 288 GB to 2,304 GB of memory per chip. Titan combines four to eight Asimov chips into one node, targeted at models beyond 16 trillion parameters and context windows beyond 10 million tokens, scaling to thousands of nodes.

Those numbers are the argument. A single Titan node carrying multiple terabytes of memory is a different machine from a rack of accelerators each rationing 192 GB of HBM.

## Why commodity memory, and what it costs you

The engineering trade is straightforward and worth stating plainly, because the marketing around memory-first architectures tends to obscure it.

HBM delivers extraordinary bandwidth per stack by sitting on an interposer beside the compute die. That requires CoWoS-class advanced packaging, which is supply-constrained, and HBM itself is expensive and supply-constrained. LPDDR5X delivers less bandwidth per device and connects conventionally — but it is manufactured in phone-scale volumes, costs a fraction as much per gigabyte, and draws less power.

Positron's claim is that with enough parallel channels and an architecture designed around them, you recover most of the bandwidth advantage while escaping both supply chains. [The company](https://positron.ai/?ref=edgewisely.com) says its next-generation systems realize more than 90% of available memory bandwidth, and that the energy profile lets the systems deploy in air-cooled or liquid-cooled facilities at varying rack densities. That last detail matters more than it sounds: [power and cooling are the binding constraint on AI data-center buildouts](https://www.edgewisely.com/ai-data-center-power-nuclear-timeline-gap/), and hardware that runs in existing air-cooled halls reaches revenue years before hardware that needs a new facility.

Baskett, in NEA's statement, framed the supply argument directly — pointing to Nvidia's Rubin Ultra memory targets being trimmed because HBM supply is not there. Treat an investor's characterization of a competitor's roadmap as an investor's characterization. But the underlying dynamic, that HBM and CoWoS allocation now gates who ships accelerators at all, is not contested by anyone in the industry.

The cost of the trade is that Positron is optimizing hard for one workload. Memory-first silicon serving trillion-parameter models with million-token contexts is an excellent bet if that is where inference demand concentrates. It is a poor bet if the market moves toward smaller distilled models where compute density matters more than capacity.

## The credibility problem, mostly solved

Inference-chip startups have a graveyard behind them, and the usual failure mode is a compelling architecture that never reaches production at a real customer. Positron's answer is Atlas, its first-generation system, which the company says is deployed in more than 50 racks at Oracle Cloud Infrastructure, with Parasail running an inference service on that capacity and Jump Trading and i3d.net among production customers.

That is the single most load-bearing fact in the announcement. Fifty-plus racks inside a hyperscaler is not a pilot. It means someone ran the procurement, the integration and the operational risk assessment and signed. [SiliconANGLE's coverage](https://siliconangle.com/2026/09/10/chipmaker-positron-nabs-875m-to-speed-up-inference-with-consumer-grade-memory/?ref=edgewisely.com) frames the round as funding the jump from that deployment to volume silicon, which is the right frame.

It also explains the valuation. A $5 billion mark on a company whose flagship chip has not taped out only makes sense if you are underwriting execution risk on generation two rather than architecture risk on generation one. Atlas is the evidence that the second is already retired.

## Who this lands on

**For Nvidia**, a single memory-first competitor is not a threat to the training franchise. The relevant question is whether inference separates into its own procurement category with its own vendor list. That has been the direction of travel all year, and [Nvidia's own moves toward custom silicon partnerships](https://www.edgewisely.com/nvidia-3-5-billion-mediatek-gambit/) suggest it agrees the inference market fragments. Positron is one of several parties arguing that the chip which trains a model should not be the chip that serves it.

**For the memory makers**, this is the more interesting signal. If memory-first architectures gain share, demand shifts from HBM — high-margin, allocated, capacity-constrained — toward LPDDR5X, where the volumes are enormous and the margins are not. Samsung, SK Hynix and Micron have built their AI narrative on the first. Positron is placing a nine-figure supply commitment on the second.

**For inference buyers**, the pitch is tokens per dollar and tokens per watt rather than raw speed. That is the correct metric and it is also the one that cuts against the incumbent's strengths. Anyone serving long-context workloads at volume should be running the arithmetic themselves, because [the gap between AI capex and AI revenue](https://www.edgewisely.com/ai-capex-revenue-gap-2026-hyperscalers/) is being closed on the cost side or not at all.

**For Positron**, the risk is now almost entirely schedule. Asimov tapes out at the end of 2026 and produces in the second half of 2027\. That is a long exposure window in a market where Nvidia ships a new architecture roughly annually and HBM supply could loosen. The company has raised enough to survive one slip. Probably not two.

## The zoom-out

Every hardware cycle eventually produces the same insight: the winning architecture is usually the one that routes around the scarcest input rather than competing for it.

Positron's case is that HBM scarcity is not a temporary supply problem the industry will engineer past, but a structural feature of AI infrastructure economics — and that a company willing to build around commodity DRAM gets a cost and power curve the incumbents cannot match without abandoning their own roadmaps. Jim Clark writing a check into memory-first silicon is a nice historical rhyme; he built a company on the premise that specialized graphics hardware would beat general-purpose compute, right up until general-purpose compute ate it.

The lesson cuts both ways, and Positron's investors surely know it.

*Scarcity defines architecture. The question is never which component is best — it is which one you can actually buy.*

## Frequently Asked Questions

### How much did Positron AI raise and at what valuation?

Positron AI raised $875 million in September 2026 at a $5 billion post-money valuation. The financing came in two tranches: a $375 million Series C at a $3.5 billion pre-money valuation, and a Series C-1 of up to $500 million led by NEA and Netscape co-founder Jim Clark.

### What makes Positron's inference chips different?

Positron builds memory-first inference silicon using commodity LPDDR5X rather than high-bandwidth memory. That avoids the constrained HBM and CoWoS advanced-packaging supply chains, lowers cost and power per gigabyte, and allows far larger memory capacity per chip — 288 GB to 2,304 GB on its forthcoming Asimov silicon.

### When will Positron's Asimov chip ship?

Asimov is scheduled to tape out on TSMC's N3P process at the end of 2026, with production targeted for the second half of 2027\. It powers Titan, a system combining four to eight Asimov chips per node, designed for models above 16 trillion parameters and context windows beyond 10 million tokens.

### Does Positron have paying customers today?

Yes. Positron says its first-generation Atlas system is deployed across more than 50 racks at Oracle Cloud Infrastructure, where partner Parasail runs an inference service on that capacity. The company also names Jump Trading and i3d.net as Atlas production customers, giving it deployment experience ahead of Asimov.

---

*Editor's note — sources:* [*Positron AI's funding announcement*](https://www.prnewswire.com/news-releases/positron-ai-raises-875-million-at-a-5-billion-valuation-to-bring-its-next-generation-inference-silicon-to-market-302874601.html?ref=edgewisely.com) *(Sept 10, 2026);* [*SiliconANGLE*](https://siliconangle.com/2026/09/10/chipmaker-positron-nabs-875m-to-speed-up-inference-with-consumer-grade-memory/?ref=edgewisely.com)*;* [*Converge Digest*](https://convergedigest.com/positron-ai-raises-875m-asimov-inference-silicon/?ref=edgewisely.com)*;* [*Positron AI*](https://positron.ai/?ref=edgewisely.com)*. Additional coverage: Reuters via Investing.com. Bandwidth-utilization and tokens-per-watt figures are company claims and have not been independently benchmarked.*