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# Samsung Moves the Processor Into the Memory Chip
- URL: https://www.edgewisely.com/samsung-lpddr5x-pim-ai-memory-explained/
- Published: 2026-08-27T05:11:07.000Z
- Updated: 2026-08-27T05:11:07.000Z
- Description: Samsung's answer to AI's memory bottleneck isn't a faster chip next to the memory. It's moving a sliver of the chip inside the memory itself.
- Author: John Karpentar
- Tags: Chips, Deep Tech

# Samsung Moves the Processor Into the Memory Chip

### LPDDR5X-PIM tripled AI inference throughput in Samsung's own tests by putting a small amount of logic where the data already lives — no new circuit board required.

**The most expensive bottleneck in AI hardware right now isn't compute. It's moving data back and forth between memory and the processor fast enough to keep that compute busy. Samsung's answer, unveiled at Hot Chips 2026, is to stop moving the data at all — and do a piece of the math right where it's stored.**

Samsung detailed LPDDR5X-PIM, the industry's first LPDDR memory chip with processing-in-memory logic built in, at the Hot Chips conference and, earlier in August, at the Future of Memory and Storage event in Santa Clara. The design places a small logic unit directly alongside DRAM cells, letting basic calculations happen inside the memory itself instead of shuttling every bit of data out to a separate processor and back, according to [Samsung's own technical presentation](https://news.samsungsemiconductor.com/global/samsung-unveils-next-gen-3d-memory-vision-at-fms-2026-charting-the-future-of-ai-infrastructure/?ref=edgewisely.com) and [Tom's Hardware's coverage of the Hot Chips session](https://www.tomshardware.com/pc-components/dram/hot-chips-2026-samsung-makes-lpddr5x-smart-with-logic-unit-in-memory-lpddr5x-pim-is-3-01x-faster-than-lpddr5x-in-ai-inference-with-8x-the-bandwidth?ref=edgewisely.com).

## The numbers behind the claim

In Samsung's preliminary testing, LPDDR5X-PIM delivered 2.28 times faster model runtime and 3.01 times greater token throughput compared to conventional LPDDR5X. Peak bandwidth jumped from 76.8 GB/s on standard LPDDR5X-9600 to a theoretical 614 GB/s in PIM mode — an eightfold increase, achieved inside the same 561-ball package device makers already design around, meaning no PCB redesign is required to adopt it.

The most concrete demonstration came from running Meta's Llama 3.1 8B model on an edge AI accelerator: token throughput rose from 27 to 81.3 tokens per second, roughly a threefold improvement, according to [ServeTheHome's writeup of the Hot Chips presentation](https://www.tomshardware.com/pc-components/dram/hot-chips-2026-samsung-makes-lpddr5x-smart-with-logic-unit-in-memory-lpddr5x-pim-is-3-01x-faster-than-lpddr5x-in-ai-inference-with-8x-the-bandwidth?ref=edgewisely.com). Samsung has been explicit that these results are preliminary — optimization work, including accuracy tuning, is still underway, so the numbers should be read as a demonstration of the architecture's potential rather than a shipping-product guarantee.

## Why this problem is worth solving in memory, not silicon

AI inference, especially for the smaller models increasingly run on laptops, phones, and edge accelerators, is often bottlenecked less by how fast a processor can compute than by how fast it can retrieve the weights and activations it needs from memory. That's the "memory wall" that's driven the entire high-bandwidth memory boom of the past several years — and it's also what's made HBM one of the most expensive, supply-constrained components in the entire AI hardware stack.

Processing-in-memory attacks that constraint from a different angle: instead of building a faster highway between memory and processor, it eliminates some of the trips entirely by doing simple operations — the kind that dominate inference workloads — right where the data already sits. Samsung positioned LPDDR5X-PIM explicitly as a complement to HBM rather than a replacement. HBM still offers far more raw bandwidth and remains the standard for large-scale model training and high-throughput cloud inference; LPDDR5X-PIM is aimed at a different, lower-power tier — client devices, mobile, and edge accelerators — where HBM's cost and power profile don't fit anyway.

## Who this actually helps

For device makers building laptops, phones, and edge AI accelerators, LPDDR5X-PIM offers a genuinely rare thing in hardware: a substantial performance jump that drops into existing package and board designs rather than forcing a redesign. That matters commercially — it lowers the barrier for OEMs to actually adopt the technology quickly, rather than waiting out a multi-year design cycle.

For cloud and hyperscale AI infrastructure, the near-term relevance is more indirect. LPDDR5X-PIM isn't competing with HBM4E or HBM5 for training clusters; it's addressing a cost and power problem in a different part of the market, which means it doesn't do much to relieve the HBM supply crunch that's been constraining large model training all year. Samsung's own roadmap, spanning HBM4E, HBM5, LPDDR5X-PIM, and enterprise storage lines like PM1763, makes clear the company sees these as separate, parallel bets on different layers of the AI memory stack rather than one technology substituting for another.

For competitors — SK Hynix and Micron chief among them — the announcement is a marker in an increasingly crowded race to find the next axis of differentiation in AI memory now that HBM leadership alone isn't guaranteed to be the deciding factor. If processing-in-memory proves durable at the edge, it becomes another front where memory makers compete, on top of raw bandwidth and capacity.

## The caveat that matters

Samsung's own framing is careful here, and worth taking seriously: these are preliminary results from concept demonstrations at industry conferences, not benchmarks from shipping products in customer hands. Accuracy tuning, real-world workload diversity, and the software ecosystem needed to actually exploit in-memory compute (compilers, frameworks, and driver support) are all still being built out. Processing-in-memory as a category has been discussed in academic and industry circles for years without achieving mass commercial adoption, partly because getting software to actually use the in-memory logic efficiently is a harder problem than the hardware itself.

## Why it matters

The AI hardware conversation has been dominated by HBM capacity and Nvidia's roadmap for so long that it's easy to miss the parallel fight happening one tier down, in the memory that actually ships inside the devices people use every day. Samsung's LPDDR5X-PIM is a bet that the next meaningful efficiency gain in edge AI won't come from a faster processor or more memory bandwidth in the traditional sense — it'll come from blurring the line between the two. Whether it becomes a shipping product that changes how phones and laptops run AI, or another promising processing-in-memory demonstration that stalls at the software layer, is the question the next year of Samsung's roadmap will have to answer.

## Frequently Asked Questions

### What is LPDDR5X-PIM?

LPDDR5X-PIM is Samsung's processing-in-memory memory chip, the industry's first LPDDR design with logic built directly alongside the DRAM cells. It performs basic calculations inside the memory itself, reducing the data movement that typically bottlenecks AI inference, and was detailed at Hot Chips 2026 and FMS 2026.

### How much faster is LPDDR5X-PIM than standard LPDDR5X?

In Samsung's preliminary tests, LPDDR5X-PIM delivered 2.28 times faster model runtime and 3.01 times greater AI token throughput than conventional LPDDR5X, with peak bandwidth rising roughly eightfold to a theoretical 614 GB/s.

### Does LPDDR5X-PIM replace HBM?

No. Samsung describes it as a complement, not a replacement. HBM still offers far greater raw bandwidth and remains the standard for large-scale AI model training and cloud inference; LPDDR5X-PIM targets a different, lower-power tier: mobile, client devices, and edge AI accelerators.

### Is LPDDR5X-PIM available in products yet?

Not yet. Samsung has described the current results as preliminary, from concept demonstrations at Hot Chips and FMS 2026, with optimization work including accuracy tuning still underway. No commercial shipping timeline has been announced.

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Editor's note — sources: Samsung Semiconductor Global Newsroom; Tom's Hardware; ServeTheHome; Digitimes.