The Leading Edge Belongs to AI Now

Process allocation is the closest thing the chip industry has to a revealed preference. It just changed.

For roughly fifteen years, one customer stood at the front of the queue at TSMC. When a new process node came out of development, Apple took it first — for the iPhone, at enormous volume, with a launch date that functioned as an industry metronome. Everyone else got the node in year two, at better yields and lower prices, and built their businesses around that cadence.

That queue has reordered. TSMC's A16 process — its first Angstrom-class node, entering volume production in the second half of 2026 — is expected to be adopted first by AI chips rather than smartphones. TSMC executives have said as much. And reporting suggests Apple is skipping A16 entirely, waiting for A14 instead.

This is my read, and it is an argument rather than a report: the change in who goes first is a bigger deal than the node itself, because process priority reveals who the foundry believes its future depends on. For fifteen years that answer was consumer volume. It is now AI compute — and that reordering will show up in prices, in roadmaps, and eventually in the phone in your pocket.

What A16 actually is

Start with the technical facts, because the argument rests on them.

A16 is TSMC's 1.6nm-class node. Per TSMC's own description, it combines nanosheet transistors with a backside power rail — a structural change in how power reaches the transistor. Conventional chips route power and signal through the same congested stack of metal layers above the transistor. A backside network moves power delivery underneath, freeing the front side for signal routing and cutting resistance on the power path.

TSMC calls its implementation Super Power Rail, and unlike simpler backside schemes it connects directly to each transistor's source and drain, which is harder to manufacture and better on performance. Against N2P, TSMC's enhanced 2nm process, the company cites an 8–10% speed improvement at the same voltage, or a 15–20% power reduction at the same speed, plus roughly 8–10% higher density.

Those are respectable numbers. They are not, by historical standards, spectacular. A single-digit density gain would have been a disappointing node in 2010. What makes A16 significant is not the magnitude of the improvement but its shape — and who that shape is for.

The improvement is aimed at AI, not phones

Backside power delivery is a solution to a specific problem: chips that are simultaneously enormous, power-hungry, and dense with signal routing. That describes an AI accelerator almost perfectly. A large GPU or training chip draws hundreds of watts across a huge die, and the metal layers above the transistors are contested territory between power distribution and the interconnect that moves data between compute units. Relieving that congestion is worth real performance.

It describes a smartphone SoC much less well. Phone silicon is small, thermally constrained by a passive enclosure, and battery-limited. It benefits from density and efficiency, certainly — but backside power delivery adds process complexity, cost, and yield risk to solve a routing problem a phone chip has in far milder form.

So when Tom's Hardware described A16 as tailored for AI and HPC processors with complex signal wiring and dense power networks, that is not marketing framing. It is an accurate description of who the node was engineered for. And if reports of Apple skipping to A14 hold up, the reason is not caution. It is that A16's headline feature does not earn its cost in a phone.

That is the reordering. Not that AI chips outbid smartphones for early capacity, but that the node itself was designed around AI's constraints first.

Why this took fifteen years to happen

The old arrangement was economically airtight while it lasted. Leading-edge nodes cost billions to develop and require enormous volume to amortize. Smartphones supplied that volume — hundreds of millions of units annually, on an annual refresh, from a customer with the margins to pay a premium for being first. No other market came close.

Two things changed.

The first is that AI silicon stopped being a niche. Data-center accelerators now command wafer volumes and, more importantly, per-wafer economics that phone SoCs cannot match. An AI accelerator sells for a multiple of a phone chip's price. When your customer's product carries that kind of margin, they will pay for early access to a node in a way that a $60 smartphone SoC never could. The same gravity has already pulled memory manufacturers into multi-billion-dollar reallocations toward AI-grade capacity.

The second is that phone silicon ran out of demand for the frontier. Modern phone processors are not the limiting factor in phone experience, and have not been for years. Battery, thermals, camera, and software matter more than another 8% of transistor density. That is why skipping a node is a rational decision for Apple rather than a concession — the marginal value of being first has fallen below the marginal cost.

Put those together and the queue reorders itself without anyone deciding it should.

What follows from this

Leading-edge pricing loses its historical discipline. For fifteen years, the first customer on a node was a high-volume manufacturer with brutal cost sensitivity, which anchored what leading-edge capacity could be charged for. AI buyers are far less price-sensitive because the chips they build sell into a market with severe supply constraints and extraordinary margins. Expect the premium for early node access to widen, and expect it to stay wide as long as accelerator demand does.

Node development follows the money. Process roadmaps are shaped years ahead by anticipated customer requirements. If AI is the anchor tenant, subsequent nodes will keep optimizing for large dies, high power, and dense interconnect — the AI profile. Mobile and embedded chips will inherit those nodes rather than drive them, and will pay complexity costs for features they only partly need. This is exactly the dynamic that once pushed server and HPC silicon into the trailing position, running in reverse.

Everything downstream of leading-edge access gets more strategic. If early capacity is scarce, expensive, and allocated to AI, then a company's relationship with TSMC becomes a competitive asset in its own right. That advantages the largest buyers and disadvantages everyone building custom silicon at moderate scale — including, notably, the wave of AI startups designing their own accelerators to escape Nvidia's pricing. Escaping the chip vendor does not escape the foundry. It is also why betting on fixed-function silicon over flexibility is a wager on process access as much as on architecture.

Intel and Samsung get a narrower opening than it appears. Both are pursuing their own backside-power implementations, and the reordering theoretically creates room for a second source. But if AI is the customer that matters, the bar is not "a competitive node." It is a competitive node with the yields, packaging, and advanced-capacity throughput that AI accelerators require at volume, from a supplier those customers are willing to depend on. That is a higher bar than process parity.

Where this argument could be wrong

Two ways, and both are worth taking seriously.

The first is that the reports are ahead of the facts. TSMC does not comment on individual customers, and specific claims about Nvidia being first or Apple skipping to A14 are reporting rather than confirmation. TSMC's own public commitment is volume production in the second half of 2026, and its executives' guidance that AI chip makers are likely early adopters. Those are the facts. The rest is well-sourced inference, and inference has been wrong about foundry roadmaps before.

The second is more fundamental: AI capital expenditure could normalize. The current willingness to pay almost anything for leading-edge accelerator capacity rests on an investment cycle that is extraordinary by any historical measure. If that spending settles into something more like a normal infrastructure market, the economics that put AI at the front of the queue soften considerably — and volume consumer products, which are structurally durable in a way that capex cycles are not, look attractive again.

I do not think that reversal happens quickly. But anyone building a decade-long strategy on the assumption that AI permanently owns the leading edge should notice that the assumption is only about three years old.

The zoom-out

Process nodes are the closest thing the technology industry has to a revealed preference. Marketing is cheap and roadmaps are aspirational, but capacity allocation is a physical commitment made years ahead with billions of dollars behind it. When a foundry designs its most advanced node around one customer profile rather than another, it is telling you which market it believes will still be paying premium prices in 2030.

For fifteen years, the answer was the phone in your pocket. Everything else in semiconductors — pricing, packaging, roadmaps, the shape of the supply chain — arranged itself around that fact.

The answer has changed. It is worth watching what rearranges next.

Follow the node allocation, not the keynote. The wafers know first.

Frequently Asked Questions

What is TSMC's A16 process?

A16 is TSMC's 1.6nm-class node and its first Angstrom-class production process, scheduled for volume production in the second half of 2026. It combines nanosheet transistors with Super Power Rail, a backside power delivery network that connects directly to each transistor's source and drain, improving performance and power efficiency for large, power-dense chips.

How much better is A16 than TSMC's 2nm process?

Compared with N2P, TSMC's enhanced 2nm node, TSMC cites an 8% to 10% increase in computing speed at the same voltage, or a 15% to 20% reduction in power consumption at the same speed, along with roughly 8% to 10% higher chip density. These are solid but not historically dramatic generational gains.

Why would AI chips adopt A16 before smartphones?

A16's backside power rail specifically addresses routing congestion in large, high-power dies — a defining characteristic of AI accelerators and much less pressing in small, thermally constrained smartphone processors. TSMC executives have indicated AI chip makers are likely to be first adopters, reversing fifteen years of mobile-first node introduction.

Does Apple really plan to skip A16?

Reports indicate Apple intends to move from 2nm-class processes directly to A14 rather than adopting A16. TSMC does not comment on individual customers, so this remains reporting rather than confirmation. The rationale is economic: A16's headline backside-power feature delivers less benefit in a phone SoC than in a data-center accelerator.

Editor's note — sources:

• TSMC, A16 technology page — https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_A16
• Tom's Hardware — https://www.tomshardware.com/tech-industry/tsmc-unveils-16nm-process-technology-with-backside-power-delivery-rivals-intels-competing-design
• TweakTown — https://www.tweaktown.com/news/109173/tsmcs-first-customer-for-next-gen-a16-process-is-nvidia-apple-skips-a16-directly-to-a14-node/index.html